
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   16:06:20 03/04/2012
-- Design Name:   FU
-- Module Name:   C:/Xilinx92i/PROJECTAIC/tb_FU.vhd
-- Project Name:  Procesador
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: FU
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_arith.all;

ENTITY tb_FU_vhd IS
END tb_FU_vhd;

ARCHITECTURE behavior OF tb_FU_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT FU
	PORT(
		fu_pc_sel : in  STD_LOGIC;--inutil momentaneamente
           fu_mux10_sel : in  STD_LOGIC;
           fu_mux3_sel : in  STD_LOGIC_VECTOR (2 downto 0);
           clk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           offset : in  STD_LOGIC_VECTOR (7 downto 0);
           address : in  STD_LOGIC_VECTOR (9 downto 0);
           st_out : in  STD_LOGIC_VECTOR (9 downto 0);
           pc_in_reg_interrupt : in  STD_LOGIC_VECTOR (9 downto 0);
           pc_in : in  STD_LOGIC_VECTOR (9 downto 0);
           pc_out : out  STD_LOGIC_VECTOR (9 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL fu_pc_sel :  std_logic := '0';
	SIGNAL fu_mux10_sel :  std_logic := '0';
	SIGNAL clk :  std_logic := '0';
	SIGNAL clr :  std_logic := '0';
	SIGNAL fu_mux3_sel :  std_logic_vector(2 downto 0) := (others=>'0');
	SIGNAL offset :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL address :  std_logic_vector(9 downto 0) := (others=>'0');
	SIGNAL st_out :  std_logic_vector(9 downto 0) := (others=>'0');
	SIGNAL pc_in_reg_interrupt :  std_logic_vector(9 downto 0) := (others=>'0');
	SIGNAL pc_in :  std_logic_vector(9 downto 0) := (others=>'0');

	--Outputs
	SIGNAL pc_out :  std_logic_vector(9 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: FU PORT MAP(
		fu_pc_sel => fu_pc_sel,
		fu_mux10_sel => fu_mux10_sel,
		fu_mux3_sel => fu_mux3_sel,
		clk => clk,
		clr => clr,
		offset => offset,
		address => address,
		st_out => st_out,
		pc_in_reg_interrupt => pc_in_reg_interrupt,
		pc_in => pc_in,
		pc_out => pc_out
	);


	clk <= not clk after 25 ns; --periodo de 50 ns;

	tb : PROCESS
	BEGIN
		
		clr <= '0';
		pc_in <= (others => '0');--inicializamos el pc_in a 0
		
		wait for 49 ns;
		
		assert (pc_out = conv_std_logic_vector(0,10))
				report "Error en el clear"
				severity FAILURE;
		
		clr <= '1';
		wait for 50 ns;
		
		fu_mux3_sel <= "000";--a cero
		wait for 50 ns;		
		assert (pc_out = conv_std_logic_vector(0,10))
				report "Error en la opcion de 0 del multiplexor 3"
				severity FAILURE;
		
		
		
		fu_mux3_sel <= "001";--del sumador 2

			offset <= conv_std_logic_vector(10,8);
			fu_mux10_sel <= '1';--sumo el offset
			
			wait for 50 ns;
			assert (pc_out = pc_in + "00" & offset)
					report "Error en el offset del mux 10"
					severity FAILURE;
	
	
			fu_mux10_sel <= '0';--sumo 1
			wait for 50 ns;
			assert (pc_out = pc_in + 1)
					report "Error en el autoincremento del mux 10"
					severity FAILURE;



		
		address <= conv_std_logic_vector(10,10);
		fu_mux3_sel <= "010";--address
		wait for 50 ns;
		assert (pc_out = conv_std_logic_vector(8,10) + pc_in)
				report "Error en la carga del address"
				severity FAILURE;
		
		
		
		st_out <= conv_std_logic_vector(100,10);		
		fu_mux3_sel <= "011";--pila
		wait for 50 ns;
		assert (pc_out = conv_std_logic_vector(100,10))
				report "Error en la opcion de 3 del multiplexor 3"
				severity FAILURE;
		
		
		
		pc_in_reg_interrupt <= conv_std_logic_vector(127,10);
		fu_mux3_sel <= "100";--interrupcion
		wait for 50 ns;
		assert (pc_out = conv_std_logic_vector(127,10))
				report "Error en la opcion de 4 del multiplexor 3"
				severity FAILURE;
		
	

		report ("**********TESTS DE FU SUPERADOS**********")
		severity NOTE;

		
		wait; -- will wait forever
	END PROCESS;

END;
